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Ordering number : ENN7825
LC87F74C8A
Overview
CMOS IC FROM 128K-byte, RAM 4096-byte on chip
8-bit 1-chip Microcontroller
The LC87F74C8A is an 8-bit single chip microcontroller with the following on-chip functional blocks : * CPU : operable at a minimum bus cycle time of 100ns * 128K-bytes flash ROM (on-board rewritable) * On-chip RAM : 4096-bytes * LCD controller/driver * Two high performance 16-bit timer/counters (can be divided into 8-bit units) * 16-bit timer/PWM (can be divided into two 8-bit timers) * Four 8-bit timer with prescalers * Timer for use as date/time clock * Synchronous serial I/O port (with automatic block transmit/receive function) * Asynchronous/synchronous serial I/O port * 15-channel x 8-bit AD converter * High-speed clock counter * System clock divider * Small signal detector * 20-source 10-vectored interrupt system All of the above functions are fabricated on a single chip.
Features
Flash ROM * Single 5V power supply, on-board writable * Block erase in 128-byte units * 131072 x 8-bits (LC87F74C8A) Random access memory (RAM) * 4096 x 9-bits (LC87F74C8A) Minimum bus cycle time * 100ns (10MHz) Note : The bus cycle time indicates ROM read time.
Ver.1.02 82202
83004 JO IM No.7825-1/21
LC87F74C8A
Minimum instruction cycle time * 300ns (10MHz) Ports * Input/output ports Data direction programmable for each bit individually : 26 (P1n, P30 to P35, P70 to P73, P8n) Data direction programmable in nibble units : 8 (P0n) (When N-channel open drain output is selected, data can be input in bit units.) * Input ports : 2 (XT1, XT2) * LCD ports Segment output : 48 (S00 to S47) Common output : 4 (COM0 to COM3) Bias terminals for LCD driver 3 (V1 to V3) Other functions Input/output ports : 48 (PAn, PBn, PDn, PEn, PFn) Input ports : 7 (PLn) * Oscillator pins : 2 (CF1, CF2) * Reset pin : 1 (RES) * Power supply : 6 (VSS1 to 3, VDD1 to 3) LCD controller * Seven display modes are available (static, 1/2, 1/3, 1/4 duty x 1/2, 1/3 bias) * Segment output and common output can be switched to general purpose input/output ports. Small signal detection (MIC signals etc) * Counts pulses with the level which is greater than a preset value * 2-bit counter Timer * Timer 0 : 16-bit timer/counter with capture register Mode 0 : 2-channel 8-bit timer with programmable 8-bit prescaler and 8-bit capture register Mode 1 : 8-bit timer with 8-bit programmable prescaler and 8-bit capture register + 8-bit Counter with 8-bit capture register Mode 2 : 16-bit timer with 8-bit programmable prescaler and 16-bit capture register Mode 3 : 16-bit counter with 16-bit capture register * Timer 1 : PWM/16-bit timer/counter with toggle output function Mode 0 : 2-channel 8-bit timer/counter (with toggle output) Mode 1 : 2-channel 8-bit PWM Mode 2 : 16-bit timer/counter (with toggle output) Toggle output from lower 8-bits is also possible. Mode 3 : 16-bit timer (with toggle output) Lower order 8-bits can be used as PWM. * Timer 4 : 8-bit timer with 6-bit prescaler * Timer 5 : 8-bit timer with 6-bit prescaler * Timer 6 : 8-bit timer with 6-bit prescaler * Timer 7 : 8-bit timer with 6-bit prescaler * Base Timer 1. The clock signal can be selected from any of the following : Sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output from timer 0 2. Interrupts of five different time intervals are possible. High speed clock counter * Countable up to 20MHz clock (when using 10MHz main clock) * Real time output
No.7825-2/21
LC87F74C8A
Serial interface * SIO0 : 8-bit synchronous serial interface 1. LSB first/MSB first is selectable 2. Internal 8-bit baud-rate generator (fastest clock period 4/3 tCYC) 3. Consecutive automatic data communication (1 to 256-bits) * SIO1 : 8-bit asynchronous/synchronous serial interface Mode 0 : Synchronous 8-bit serial IO (2-wire or 3-wire, transmit clock 2 to 512 tCYC) Mode 1 : Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8 to 2048 tCYC) Mode 2 : Bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tCYC) Mode 3 : Bus mode 2 (start detection, 8 data bits, stop detection) AD converter * 8-bits x 15-channels Remote control receiver circuit (connected to P73/INT3/T0IN terminal) * Noise rejection function (noise rejection filter's time constant can be selected from 1/32/128 tCYC) Watchdog timer * The watching time period is determined by an external RC. * Watchdog timer can produce interrupt or system reset Interrupts : 18 sources, 10 vectors 1. Three priority (low, high and highest) multiple interrupts are supported. During interrupt handling, an equal or lower priority interrupt request is postponed. 2. If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence. In the case of equal priority levels, the vector with the lowest address takes precedence.
No. 1 2 3 4 5 6 7 8 9 10 Vector 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Selectable Level X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L INT0 INT1 INT2/T0L/INT4 INT3/Base timer/INT5 T0H T1L/T1H SIO0 SIO1 ADC/MIC/T6/T7 Port 0/T4/T5 Interrupt Signal
* Priority Level : X>H>L * For equal priority levels, vector with lowest address takes precedence. Subroutine stack levels : 2048 levels max. Stack is located in RAM. Multiplication and division * 16-bit x 8-bit (executed in 5 cycles) * 24-bit x 16-bit (12 cycles) * 16-bit / 8-bit (8 cycles) * 24-bit / 16-bit (12 cycles) Oscillation circuits * On-chip RC oscillation for system clock use. * CF oscillation for system clock use. (Rf built in, Rd external) * Crystal oscillation low speed system clock use. (Rf built in, Rd external) * On-chip frequency variable RC oscillation circuit for system clock use.
No.7825-3/21
LC87F74C8A
System clock divider * Low power consumption operation is available * Minimum instruction cycle time (300ns, 600ns, 1.2s, 2.4s, 4.8s, 9.6s, 19.2s, 38.4s, 76.8s can be switched by program (when using 10MHz main clock) Standby function * HALT mode HALT mode is used to reduce power consumption. During the HALT mode, program execution is stopped but peripheral circuits keep operating (some parts of serial transfer operation stop.) 1. Oscillation circuits are not stopped automatically. 2. Released by the system reset or interrupts. * HOLD mode HOLD mode is used to reduce power consumption. Program execution and peripheral circuits are stopped. 1. CF, RC and crystal oscillation circuits stop automatically. 2. Released by any of the following conditions. 1. Low level input to the reset pin 2. Specified level input to one of INT0, INT1, INT2, INT4, INT5 3. Port 0 interrupt * X'tal HOLD mode X'tal HOLD mode is used to reduce power consumption. Program execution is stopped. All peripheral circuits except the base timer are stopped. 1. CF and RC oscillation circuits stop automatically. 2. Crystal oscillator operation is kept in its state at HOLD mode inception. 3. Released by any of the following conditions 1. Low level input to the reset pin 2. Specified level input to one of INT0, INT1, INT2, INT4, INT5 3. Port 0 interrupt 4. Base-timer interrupt Package * QIP100E * TQFP100 Development tools * Evaluation chip * Emulator
: LC876093 : EVA62S + ECB876600 (Evaluation chip board) + SUB877400 + POD100QFP or POD100SQFP (Type B) : ICE-B877300 + SUB877400 + POD100QFP or POD100SQFP (Type B) * Flash ROM write adapter : W87FQ100 or W87FSQ100
Same package and pin assignment as mask ROM version. 1. LC877400 series options can be set using flash ROM data. Thus the board used for mass production can be used for debugging and evaluation without modifications. 2. If the program for the mask ROM version is used, the usable ROM/RAM capacity is the same as the mask ROM version.
No.7825-4/21
unit : mm 3151A
Pin Assignment
Package Dimensions
P06 P07 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7/MICIN P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN P73/INT3/T0IN S0/PA0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
V2/PL5/AN13 V1/PL4/AN12 COM0/PL0 COM1/PL1 COM2/PL2 COM3/PL3 P30/INT4/T1IN P31/INT4/T1IN VSS3 VDD3 P32/INT4/T1IN P33/INT4/T1IN P34/INT5/T1IN P35/INT5/T1IN P00 P01 P02 P03 P04 P05 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
LC87F74C8A
LC87F74C8A
unit : mm 3274
Package Dimensions
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 V3/PL6/AN14 S47/PF7 S46/PF6 S45/PF5 S44/PF4 S43/PF3 S42/PF2 S41/PF1 S40/PF0 S39/PE7 S38/PE6 S37/PE5 S36/PE4 S35/PE3 S34/PE2 S33/PE1 S32/PE0 S31/PD7 S30/PD6 S29/PD5 S28/PD4 S27/PD3 S26/PD2 S25/PD1 S24/PD0 VSS2 VDD2 S23/PC7 S22/PC6 S21/PC5
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 S20/PC4 S19/PC3 S18/PC2 S17/PC1 S16/PC0 S15/PB7 S14/PB6 S13/PB5 S12/PB4 S11/PB3 S10/PB2 S9/PB1 S8/PB0 S7/PA7 S6/PA6 S5/PA5 S4/PA4 S3/PA3 S2/PA2 S1/PA1
Top view
SANYO:QIP100E
No.7825-5/21
LC87F74C8A
S47/PF7 V3/PL6/AN14 V2/PL5/AN13 V1/PL4/AN12 COM0/PL0 COM1/PL1 COM2/PL2 COM3/PL3 P30/INT4/T1IN P31/INT4/T1IN VSS3 VDD3 P32/INT4/T1IN P33/INT4/T1IN P34/INT5/T1IN P35/INT5/T1IN P00 P01 P02 P03 P04 P05 P06 P07 P10/SO0
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
S46/PF6 S45/PF5 S44/PF4 S43/PF3 S42/PF2 S41/PF1 S40/PF0 S39/PE7 S38/PE6 S37/PE5 S36/PE4 S35/PE3 S34/PE2 S33/PE1 S32/PE0 S31/PD7 S30/PD6 S29/PD5 S28/PD4 S27/PD3 S26/PD2 S25/PD1 S24/PD0 VSS2 VDD2 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
LC87F74C8A
S23/PC7 S22/PC6 S21/PC5 S20/PC4 S19/PC3 S18/PC2 S17/PC1 S16/PC0 S15/PB7 S14/PB6 S13/PB5 S12/PB4 S11/PB3 S10/PB2 S9/PB1 S8/PB0 S7/PA7 S6/PA6 S5/PA5 S4/PA4 S3/PA3 S2/PA2 S1/PA1 S0/PA0 P73/INT3/T0IN
P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7/MICIN P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Top view
SANYO:TQFP100
No.7825-6/21
LC87F74C8A
System Block Diagram
Interrupt Control
IR
PLA
Stand-by Control
Flach ROM
CF RC MRC X'tal Clock Generator
PC
Bus Interface
ACC
SIO0
Port 0
B Register
SIO1 Timer 0 (High-speed clock counter)
Port 1
C Register
Port 3 ALU
Timer 1
Port 7
Base Timer
Port 8
PSW
LCD Controller INT0 to 5 Noise Rejection Filter
ADC
RAR
Weak Signal Detector
RAM
Timer 4
Timer 6
Stack Pointer
Timer 5
Timer 7
Watch Dog Timer
No.7825-7/21
LC87F74C8A
Pin Description
Pin name VSS1, VSS2, VSS3 VDD1, VDD2, VDD3 Port 0 P00 to P07 I/O I/O Power supply (-) Power supply (+) * 8-bit input/output port * Data direction programmable in nibble units * Use of pull-up resistor can be specified in nibble units * Input for HOLD release * Input for port 0 interrupt Port 1 P10 to P17 I/O * 8-bit input/output port * Data direction programmable for each bit * Use of pull-up resistor can be specified for each bit individually * Other pin functions P10 : SIO0 data output P11 : SIO0 data input or bus input/output P12 : SIO0 clock input/output P13 : SIO1 data output P14 : SIO1 data input or bus input/output P15 : SIO1 clock input/output P16 : Timer 1 PWML output P17 : Timer 1 PWMH output/Buzzer output Port 3 P30 to P35 I/O * 6-bit input/output port * Data direction can be specified for each bit * Use of pull-up resistor can be specified for each bit individually * Other functions P30 to p33 : INT4 input/HOLD release input/timer 1 event input Timer 0L capture input/Timer 0H capture input P34 to P35 : INT5 input/HOLD release input/timer 1 event input Timer 0L capture input/Timer 0H capture input * Interrupt detection selection Rising INT4 INT5 Port 7 P70 to P73 I/O * 4-bit input/output port * Data direction can be specified for each bit * Use of pull-up resistor can be specified for each bit individually * Other functions P70 : INT0 input/HOLD release input/Timer 0L capture input/output for watchdog timer P71 : INT1 input/HOLD release input/Timer 0H capture input P72 : INT2 input/HOLD release input/timer 0 event input/Timer 0L capture input P73 : INT3 input (noise rejection filter attached) /timer 0 event input/Timer 0H capture input AD input port : AN8 (P70), AN9 (P71) * Interrupt detection selection Rising INT0 INT1 INT2 INT3 Port 8 P80 to P87 I/O * 8-bit input/output port * Input/output can be specified for each bit individually * Other functions : AD input port : AN0 to AN7 Small signal detector input port : MICIN (P87) S0/PA0 to S7/PA7 S8/PB0 to S15/PB7 S16/PC0 to S23/PC7 I/O I/O I/O * Segment output for LCD * Can be used as general purpose input/output port (PA) * Segment output for LCD * Can be used as general purpose input/output port (PB) * Segment output for LCD * Can be used as general purpose input/output port (PC) No No No Yes Yes Yes Yes Falling Yes Yes Yes Yes Rising and falling No No Yes Yes H level Yes Yes No No L level Yes Yes No No No Yes Yes Falling Yes Yes Rising and falling Yes Yes H level No No L level No No No Yes Yes Function No No Yes Option
Continued on next page.
No.7825-8/21
LC87F74C8A
Continued from preceding page.
Pin name S24/PD0 to S31/PD7 S32/PE0 to S39/PE7 S40/PF0 to S47/PF7 COM0/PL0 to COM3/PL3 V1/PL4 to V3/PL6 I/O I/O I/O I/O I/O I/O * Segment output for LCD * Can be used as general purpose input/output port (PD) * Segment output for LCD * Can be used as general purpose input/output port (PE) * Segment output for LCD * Can be used as general purpose input/output port (PF) * Common output for LCD * Can be used as general purpose input port (PL) * LCD output bias power supply * Can be used as general purpose input port (PL) * Other functions : AD input ports : AN12 to AN14 RES XT1 I I Reset terminal * Input for 32.768kHz crystal oscillation * Other functions : General purpose input port AD input port : AN10 * When not in use, connect to VDD1 XT2 I/O * Output for 32.768kHz crystal oscillation * Other functions : General purpose input port AD input port : AN11 * When not in use, set to oscillation mode and leave open CF1 CF2 I O Input terminal for ceramic oscillator Output terminal for ceramic oscillator No No No No No No No No No Function No Option
Port output Configuration
Port form and pull-up resistor options are shown in the following table. Port status can be read even when port is set to output mode.
Terminal P00 to P07 Option applies to : each bit Option 1 2 P10 to P17 each bit 1 2 P30 to P35 each bit 1 2 P70 P71 to P73 P80 to P87 S0/PA0 to S47/PF7 COM0/PL0 to COM3/PL3 V1/PL4 to V3/PL6 XT1 XT2 - - - None None None Input only Input only Output for 32.768kHz crystal oscillation None None None - - - - - None None None None None CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain Nch-open drain CMOS Nch-open drain CMOS Input only Output format Pull-up resistor Programmable None Programmable Programmable Programmable None Programmable Programmable None Programmable None (Note 1)
Note 1 : Attachment of Port 0 programmable pull-up resistors is controllable in nibble units (P00 to 03, P04 to 07). * Note 1 : Connect as follows to reduce noise on VDD. VSS1, VSS2 and VSS3 must be connected together and grounded. * Note 2 : The power supply for the internal memory is VDD1 but it uses the VDD2 as the power supply for ports. When the VDD2 is not backed up, the port level does not become "H" even if the port latch is in the "H" level. Therefore, when the VDD2 is not backed up and the port latch is "H" level, the port level is unstable in the HOLD mode, and the back up time becomes shorter because the through current runs from VDD to GND in the input buffer. If VDD2 is not backed up, output "L" by the program or pull the port to "L" by the external circuit in the HOLD mode so that the port level becomes "L" level and unnecessary current consumption is prevented.
No.7825-9/21
LC87F74C8A
Back-up Capacitors *2 LSI VDD1
Power Supply
VDD2 VDD3
VSS1 VSS2 VSS3
Absolute Maximum Ratings / Ta = 25C, VSS1 = VSS2 = VSS3 = 0V
Parameter Supply voltage Supply voltage for LCD Input voltage Input/Output voltage High level output current Total output current Peak output current IOPH(2) IOPH(3) IOAH(1) IOAH(2) IOAH(3) IOAH(4) IOAH(5) Low level output current Total output current Peak output current IOPL(1) IOPL(2) IOPL(3) IOPL(4) IOAL(1) IOAL(2) IOAL(3) IOAL(4) IOAL(5) Maximum power consumption Operating temperature range Storage temperature range Tstg Topr Pd max Port 71, 72, 73 Port A, B, C, D, E, F Port 0, 1, 32 to 35 Port 30, 31 Port 7 Port A, B, C Port D, E, F Port 0, 1, 32 to 35 Port 30, 31 Port 7, 8 Port A, B, C, D, E, F Port 0, 1, 32 to 35 Port 30, 31 Port 7, 8 Port A, B, C Port D, E, F QIP100E TQFP100 -20 -55 IOPH(1) VI VIO(1) Port L XT1, XT2, CF1, RES * Port 0, 1, 3, 7, 8 * Port A, B, C, D, E, F Port 0, 1, 3 * CMOS output selected * Current at each pin Current at each pin Current at each pin Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins Current at each pin Current at each pin Current at each pin Current at each pin Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins Ta = -20 to +70C Symbol VDD max VLCD Pins VDD1, VDD2, VDD3 V1/PL4, V2/PL5, V3/PL6 Conditions VDD1 = VDD2 = VDD3 VDD1 = VDD2 = VDD3 Limits VDD [V] min -0.3 -0.3 -0.3 -0.3 -10 -3 -5 -40 -10 -5 -25 -25 20 30 5 15 60 60 20 40 40 559 404 70 C 125 mW mA typ max +6.5 VDD VDD+0.3 VDD+0.3 V unit
No.7825-10/21
LC87F74C8A
Recommended Operating Range / Ta = -20C to +70C, VSS1 = VSS2 = VSS3 = 0V
Parameter Operating supply voltage range Supply voltage range in Hold mode Input high voltage VIH(1) VIH(2) * Port 0, 3, 8 * Port A, B, C, D, E, F, L * Port 1 * Port 71, 72, 73 * P70 port input/interrupt VIH(3) VIH(4) VIH(5) Input low voltage VIL(1) VIL(2) P87 small signal input Port 70 Watchdog timer XT1, XT2, CF1, RES * Port 0, 3, 8 * Port A, B, C, D, E, F, L * Port 1 * Port 71, 72, 73 * P70 port input/interrupt VIL(3) VIL(4) VIL(5) Operation cycle time External system clock frequency FEXCF(1) CF1 * CF2 open * System clock divider : 1/1 * External clock DUTY = 50 5% * CF2 open * System clock divider : 1/2 Oscillation frequency range (Note 1) FmCF(2) CF1, CF2 FmCF(1) CF1, CF2 10MHz ceramic resonator oscillation Refer to figure 1 4MHz ceramic resonator oscillation Refer to figure 1 FmRC FmMRC RC oscillation Frequency variable RC oscillation source oscillation FsX'tal XT1, XT2 32.768kHz crystal resonator oscillation Refer to figure 2 3.0 to 5.5 32.768 kHz 3.0 to 5.5 50 3.0 to 5.5 0.3 1.0 2.0 3.0 to 5.5 4 4.5 to 5.5 10 3.0 to 5.5 0.2 8 MHz 3.0 to 5.5 4.5 to 5.5 0.1 0.2 4 20 4.5 to 5.5 0.1 10 tCYC Port 87 small signal input Port 70 Watchdog timer XT1, XT2, CF1, RES Output disable Output disable 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 4.5 to 5.5 3.0 to 5.5 VSS VSS VSS 0.294 0.735 Output disable 3.0 to 5.5 VSS Output disable Output disable Output disable 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 Output disable 3.0 to 5.5 Output disable 3.0 to 5.5 0.3VDD +0.7 0.3VDD +0.7 0.75VDD 0.9VDD 0.75VDD VSS VDD Symbol VDD(1) VDD(2) VHD VDD1 Pins VDD1 = VDD2 = VDD3 Conditions 0.294s tCYC200s 0.735s tCYC200s Keep RAM and register data in HOLD mode. 2.0 5.5 Limits VDD [V] min 4.5 3.0 typ max 5.5 5.5 unit
VDD VDD VDD VDD 0.15VDD +0.4 0.1VDD +0.4 0.25VDD 0.8VDD -1.0 0.25VDD 200 200 s V
Note 1 : The parts value of oscillation circuit is shown in table 1 and table 2.
No.7825-11/21
LC87F74C8A
Electrical Characteristics / Ta = -20C to +70C, VSS1 = VSS2 = VSS3 = 0V
Parameter High level input current Symbol IIH(1) Pins * Port 0, 1, 3, 7, 8 * Port A, B, C, D, E, F, L Conditions * Output disabled * Pull-up resister OFF. * VIN = VDD (Including OFF state leak current of the output Tr.) IIH(2) IIH(3) RES XT1, XT2 VIN = VDD When configured as an input port VIN = VDD IIH(4) IIH(5) Low level input current IIL(1) CF1 P87/AN7/MICIN small signal input * Port 0, 1, 3, 7, 8 * Port A, B, C, D, E, F, L VIN = VDD VIN = VBIS+0.5V (VBIS : Bias voltage) * Output disabled * Pull-up resister OFF. * VIN = VSS (Including OFF state leak current of the output Tr.) IIL(2) IIL(3) RES XT1, XT2 VIN = VSS When configured as an input port VIN = VSS IIL(4) IIL(5) High level output voltage VOH(1) VOH(2) VOH(3) VOH(4) Low level output voltage VOH(5) VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) VOL(6) VOL(7) LCD output voltage regulation VODLC COM0 to COM3 VODLS S0 to S47 Port 30, 31 Port 7, 8 Port A, B, C, D, E, F CF1 P87/AN7/MICIN small signal input Port 0, 1, 3, CMOS output option Port 7 Port A, B, C, D, E, F Port 0, 1, 3 VIN = VSS VIN = VBIS-0.5V (VBIS : Bias voltage) IOH = -1.0mA IOH = -0.1mA IOH = -0.4mA IOH = -1.0mA IOH = -0.1mA IOL = 10mA IOL = 1.6mA IOL = 30mA IOL = 1mA IOL = 0.5mA IOL = 8mA IOL = 1.4mA IO = 0mA VLCD, 2/3VLCD, 1/3VLCD level output Refer to figure 8 IO = 0mA VLCD, 2/3VLCD, 1/2VLCD 1/3VLCD level output Refer to figure 8 LCD bias resistor RLCD(1) RLCD(2) Resistance per one bias resistor * Resistance per one bias resistor * 1/2R mode Resistance of pull-up MOS Tr. Hysterisis voltage VHIS(1) VHIS(2) Rpu * Port 0, 1, 3, 7 * Port A, B, C, D, E, F * Port 1, 7 * RES Port 87 small signal input VOH = 0.9VDD 4.5 to 5.5 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 15 25 40 70 0.1VDD V 0.1VDD 70 150 Refer to figure 8 3.0 to 5.5 30 k Refer to figure 8 3.0 to 5.5 60 3.0 to 5.5 0 0.2 3.0 to 5.5 0 0.2 3.0 to 5.5 3.0 to 5.5 4.5 to 5.5 3.0 to 5.5 3.0 to 5.5 4.5 to 5.5 3.0 to 5.5 4.5 to 5.5 3.0 to 5.5 4.5 to 5.5 4.5 to 5.5 3.0 to 5.5 4.5 to 5.5 3.0 to 5.5 -15 -15 VDD-1 VDD-0.5 VDD-1 VDD-1 VDD-0.5 1.5 0.4 1.5 0.4 0.4 1.5 0.4 V -8.5 -4.2 3.0 to 5.5 -1 3.0 to 5.5 -1 3.0 to 5.5 -1 3.0 to 5.5 3.0 to 5.5 4.2 8.5 15 15 A 3.0 to 5.5 1 3.0 to 5.5 1 3.0 to 5.5 1 Limits VDD [V] min typ max unit
Continued on next page.
No.7825-12/21
LC87F74C8A
Continued from preceding page.
Parameter Pin capacitance Symbol CP All pins Pins Conditions * All other terminals connected to VSS. * f = 1MHz * Ta = 25C Input sensitivity Vsen Port 87 small signal input 3.0 to 5.5 0.12VDD Vp-p 3.0 to 5.5 10 pF Limits VDD [V] min typ max unit
Serial Input/Output Characteristics / Ta = -20C to +70C, VSS1 = VSS2 = VSS3 = 0V
Parameter Cycle time Low level pulse width Input clock High level pulse width Cycle time Low level pulse width Serial clock High level pulse width Cycle time Low level pulse width Output clock High level pulse width Cycle time Low level pulse width High level pulse width Serial input Data set-up time tsDI SI0 (P11), SI1 (P14), Data hold time thDI SB0 (P11), SB1 (P14) SO0 (P10), SO1 (P13), SB0 (011), SB1 (P14) * When Port is open drain : Time delay form SIOCLK trailing edge to the SO data change * Refer to figure 6 3.0 to 5.5 1/3 tCYC +0.25 4.5 to 5.5 * Measured with respect to SI0CLK leading edge. * Refer to figure 6 4.5 to 5.5 3.0 to 5.5 4.5 to 5.5 3.0 to 5.5 0.03 0.1 0.03 0.1 1/3 tCYC +0.05 s tSCKH(4) tSCK(3) tSCKL(3) tSCKLA(2) tSCKH(3) tSCKHA(2) tSCK(4) tSCKL(4) SCK1 (P15) * CMOS output * Refer to figure 6 3.0 to 5.5 1/2 tSCK 1/2 2 SCK0 (P12) * CMOS output * Refer to figure 6 3.0 to 5.5 tSCKH(2) Symbol tSCK(1) tSCKL(1) tSCKLA(1) tSCKH(1) tSCKHA(1) tSCK(2) tSCKL(2) 3.0 to 5.5 SCK1 (P15) Refer to figure 6 3.0 to 5.5 Pins SCK0 (P12) Conditions Refer to figure 6 Limits VDD [V] min 4/3 2/3 2/3 2/3 3 2 1 1 4/3 1/2 3/4 1/2 2 tCYC tSCK tCYC typ max unit
Serial output
Output delay time
tdDO
No.7825-13/21
LC87F74C8A
Pulse Input Conditions / Ta = -20C to +70C, VSS1 = VSS2 = VSS3 = 0V
Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) INT0 (P70), INT1 (P71), INT2 (P72) INT4 (P30 to P33) INT5 (P34 to P35) tPIH(2) tPIL(2) INT3 (P73) (Noise rejection ratio is 1/1.) * Condition that interrupt is accepted * Condition that event input to timer 0 is accepted tPIH(3) tPIL(3) INT3 (P73) (Noise rejection ratio is 1/32.) * Condition that interrupt is accepted * Condition that event input to timer 0 is accepted tPIH(4) tPIL(4) INT3 (P73) (Noise rejection ratio is 1/128.) tPIL(5) tPIL(5) tPIL(6) RES MICIN (P87) * Condition that interrupt is accepted * Condition that event input to timer 0 is accepted * Condition that signal is accepted to small signal detection counter. * Condition that reset is accepted 3.0 to 5.5 200 s 3.0 to 5.5 1 3.0 to 5.5 256 3.0 to 5.5 64 tCYC 3.0 to 5.5 2 Pins Conditions * Condition that interrupt is accepted * Condition that event input to timer 0 is accepted 3.0 to 5.5 1 Limits VDD [V] min typ max unit
AD Converter Characteristics / Ta = -20C to +70C, VSS1 = VSS2 = VSS3 = 0V
Parameter Resolution Absolute precision Conversion time N ET tCAD Symbol Pins AN0 (P80) to AN7 (P87) AN8 (P70) AN9 (P71) AN10 (XT1) AN11 (XT2) AN12 (V1) AN13 (V2) AN14 (V3) AD conversion time = 64 x tCYC (ADCR2 = 1) (Note 3) 4.5 to 5.5 3.0 to 5.5 (Note 2) AD conversion time = 32 x tCYC (ADCR2 = 0) (Note 3) 4.0 to 5.5 Conditions Limits VDD [V] 3.0 to 5.5 3.0 to 5.5 15.62 (tCYC = 0.488s) 23.52 (tCYC = 0.735s) 18.82 (tCYC = 0.294s) 47.04 3.0 to 5.5 Analog input voltage range Analog port input current IAINH IAINL VAIN = VDD VAIN = VSS VAIN (tCYC = 0.735s) 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 -1 VSS min typ 8 1.5 97.92 (tCYC = 3.06s) 97.92 (tCYC = 3.06s) 97.92 (tCYC = 1.53s) 97.92 (tCYC = 1.53s) VDD 1 V A s max unit bit LSB
Note 2 : Absolute precision does not include quantizing error (1/2 LSB). Note 3 : Conversion time means time from executing AD conversion instruction to loading complete digital value to register.
No.7825-14/21
LC87F74C8A
Current Dissipation Characteristics / Ta = -20C to +70C, VSS1 = VSS2 = VSS3 = 0V
Parameter Current consumption during normal operation (Note 4) IDDOP(2) Symbol IDDOP(1) Pins VDD1 = VDD2 = VDD3 Conditions * FmCF = 10MHz Ceramic resonator oscillation * FsX'tal = 32.768kHz crystal oscillation * System clock : CF 10MHz oscillation * Frequency variable RC oscillation stopped * Internal RC oscillation stopped. * Divider : 1/1 * CF1 = 20MHz external clock * FsX'tal = 32.768kHz crystal oscillation * System clock : CF1 oscillation * Internal RC oscillation stopped. * Frequency variable RC oscillation stopped * Divider : 1/2 IDDOP(3) * FmCF = 4MHz Ceramic resonator oscillation * FsX'tal = 32.768kHz crystal oscillation * System clock : CF 4MHz oscillation IDDOP(4) * Internal RC oscillation stopped. * Frequency variable RC oscillation stopped * Divider : 1/1 IDDOP(5) * FmCF = 0Hz (No oscillation) * FsX'tal = 32.768kHz crystal oscillation IDDOP(6) * Frequency variable RC oscillation stopped * System clock : RC oscillation * Divider : 1/2 IDDOP(7) * FmCF = 0Hz (No oscillation) * FsX'tal = 32.768kHz crystal oscillation * Internal RC oscillation stopped. IDDOP(8) * System clock : 1MHz with frequency variable RC oscillation * Divider : 1/2 IDDOP(9) * FmCF = 0Hz (No oscillation) * FsX'tal = 32.768kHz crystal oscillation * System clock : 32.768kHz IDDOP(10) * Internal RC oscillation stopped. * Frequency variable RC oscillation stopped * Divider : 1/2 Current consumption during HALT mode (Note 4) IDDHALT(1) VDD1 = VDD2 = VDD3 HALT mode * FmCF = 10MHz Ceramic resonator oscillation * FsX'tal = 32.768kHz crystal oscillation * System clock : CF 10MHz oscillation * Internal RC oscillation stopped. * Frequency variable RC oscillation stopped * Divider : 1/1 IDDHALT(2) HALT mode * CF1 = 20MHz external clock * FsX'tal = 32.768kHz crystal oscillation * System clock : CF1 oscillation * Internal RC oscillation stopped. * Frequency variable RC oscillation stopped * Divider : 1/2 IDDHALT(3) HALT mode * FmCF = 4MHz ceramic resonator oscillation * FsX'tal = 32.768kHz crystal oscillation IDDHALT(4) * System clock : CF 4MHz oscillation * Internal RC oscillation stopped. * Frequency variable RC oscillation stopped * Divider : 1/1 3.0 to 4.5 1.0 5 4.5 to 5.5 2.2 6 4.5 to 5.5 5.1 13 mA 4.5 to 5.5 4.6 12 3.0 to 4.5 35 250 4.5 to 5.5 80 450 A 3.0 to 4.5 1.8 9 4.5 to 5.5 2.5 13 3.0 to 4.5 0.8 7 4.5 to 5.5 1.5 11 3.0 to 4.5 3 13 4.5 to 5.5 7 21 mA 4.5 to 5.5 17 36 4.5 to 5.5 16 35 Limits VDD [V] min typ max unit
Continued on next page.
No.7825-15/21
LC87F74C8A
Continued from preceding page.
Parameter Current consumption during HALT mode (Note 4) IDDHALT(7) IDDHALT(6) Symbol IDDHALT(5) Pins VDD1 = VDD2 = VDD3 HALT mode * FmCF = 0Hz (Oscillation stop) * FsX'tal = 32.768kHz crystal oscillation * System clock : RC oscillation * Frequency variable RC oscillation stopped * Divider : 1/2 HALT mode * FmCF = 0Hz (No oscillation) * FsX'tal = 32.768kHz crystal oscillation IDDHALT(8) * Internal RC oscillation stopped. * System clock : 1MHz with frequency variable RC oscillation * Divider : 1/2 IDDHALT(9) HALT mode * FmCF = 0Hz (Oscillation stop) * FsX'tal = 32.768kHz crystal oscillation IDDHALT(10) * System clock : 32.768kHz * Internal RC oscillation stopped. * Frequency variable RC oscillation stopped * Divider : 1/2 Current consumption during HOLD mode Current consumption during Date/time clock HOLD mode IDDHOLD(4) IDDHOLD(3) VDD1 Date/time clock HOLD mode * CF1 = VDD or open (when using external clock) * FmX'tal = 32.768kHz crystal oscillation 3.0 to 4.5 8 50 4.5 to 5.5 20 90 IDDHOLD(2) IDDHOLD(1) VDD1 HOLD mode * CF1 = VDD or open (when using external clock) 4.5 to 5.5 3.0 to 4.5 0.1 0.03 25 20 A 3.0 to 4.5 12 60 4.5 to 5.5 25 100 3.0 to 4.5 1250 3300 4.5 to 5.5 1500 3600 A 3.0 to 4.5 350 1300 4.5 to 5.5 600 1600 Conditions Limits VDD [V] min typ max unit
Note 4 : The currents through the output transistors and the pull-up MOS transistors are ignored.
F-ROM Write Characteristics / Ta = +10C to +55C, VSS1 = VSS2 = VSS3 = 0V
Parameter On-board write current Write cycle time tFW(1) Symbol IDDF(1) Pins VDD1 * 128-byte write * Including erase current * 128-byte write * Including erase current * Not including time to prepare 128-byte data 4.5 to 5.5 6.3 9 mS Conditions Limits VDD [V] 4.5 to 5.5 min typ 30 max 65 unit mA
Main System Clock Oscillation Circuit Characteristics
The characteristics in the table bellow is based on the following conditions : 1. Use the standard evaluation board SANYO has provided. 2. Use the peripheral parts with indicated value externally. 3. The peripheral parts value is a recommended value of oscillator manufacturer Table 1. Main system clock oscillation circuit characteristics using ceramic resonator
Circuit parameters Frequency Manufacturer Oscillator C1 [pF] 10MHz Murata CSTCE10M0G52-R0 CSTLS10M0G53-B0 CSTCR4M00G53-R0 CSTLS4M00G53-B0 (10) (10) (15) (15) C2 [pF] (10) (10) (15) (15) Rd1 [] 220 220 1k 470 Operating supply voltage range [V] 4.5 to 5.5 4.5 to 5.5 3.0 to 5.5 3.0 to 5.5 typ [mS] 0.05 0.05 0.05 0.05 Oscillation stabilizing time max [mS] 0.15 0.15 0.15 0.15 Built-in C1, C2 Built-in C1, C2 Built-in C1, C2 Built-in C1, C2 Notes
4MHz
Murata
The oscillation stabilizing time is a period until the oscillation becomes stable after VDD becomes higher than minimum operating voltage. (Refer to Figure 4)
No.7825-16/21
LC87F74C8A
Subsystem Clock Oscillation Circuit Characteristics
The characteristics in the table bellow is based on the following conditions : 1. Use the standard evaluation board SANYO has provided. 2. Use the peripheral parts with indicated value externally. 3. The peripheral parts value is a recommended value of oscillator manufacturer Table 2. Subsystem clock oscillation circuit characteristics using crystal oscillator
Circuit parameters Frequency Manufacturer Oscillator C3 [pF] 32.768kHz SEIKO EPSON MC-306 18 C4 [pF] 18 Rf [] OPEN Rd2 [] 560k Operating supply voltage range [V] 3.0 to 5.5 Oscillation stabilizing time typ [S] 1.553 max [S] 3.00 Notes
The oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which starts the sub-clock oscillation or after releasing the HOLD mode. (Refer to Figure 4) Notes : Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length.
CF1
CF2 Rd1
XT1
XT2
Rf
Rd2
C1
CF
C2
C3 X'tal
C4
Figure 1 Ceramic oscillation circuit
Figure 2 Crystal oscillation circuit
0.5VDD
Figure 3 AC timing measurement point
No.7825-17/21
LC87F74C8A
VDD Power VDD limit 0V Reset time RES
Internal RC Resonator tmsCF CF1, CF2
tmsXtal XT1, XT2
Operation mode
Unfixed
Reset
Instruction execution mode
Reset time and oscillation stable time
HOLD release
Without HOLD Release
HOLD release signal VALID
Internal RC Resonator tmsCF CF1, CF2
tmsXtal XT1, XT2
Operation mode
HOLD
HALT
HOLD release signal and oscillation stable time
Figure 4 Oscillation stabilizing time
No.7825-18/21
LC87F74C8A
VDD
RRES RES CRES
(Note) Select CRES and RRES value to assure that at least 200s reset time is generated after the VDD becomes higher than the minimum operating voltage.
Figure 5 Reset circuit
SIOCLK
DATAIN
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7 Data RAM transmission period (only SIO0)
DO8
tSCK tSCKL SIOCLK tsDI DATAIN tdDO DATAOUT thDI tSCKH
Data RAM transmission period (only SIO0) tSCKLA SIOCLK tsDI DATAIN tdDO DATAOUT thDI tSCKHA
Figure 6 Serial input/output wave form
No.7825-19/21
LC87F74C8A
tPIL
tPIH
Figure 7 Pulse input timing
VDD SW : ON/OFF (programmable)
RLCD RLCD RLCD RLCD VLCD RLCD RLCD 2/3VLCD RLCD 1/2VLCD RLCD 1/3VLCD RLCD RLCD GND
SW : ON (VLCD = VDD)
Figure 8 LCD bias resistor
No.7825-20/21
LC87F74C8A
PS No.7825-21/21

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